The semiconductor industry has experienced rapid growth due to continuous improvement in the integration density of a variety of electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). For the most part, this improvement in integration density has come from repeated reductions in minimum feature size (e.g., shrinking the semiconductor process node towards the sub-20 nm node), which allows more components to be integrated into a given area. As the demand for miniaturization, higher speed, and greater bandwidth, as well as lower power consumption and latency has grown recently, there has been an accompanying growth in the need for smaller and more creative packaging techniques for semiconductor dies.
Using the packaging techniques, the semiconductor dies having the electronic components may be electrically connected to an external device, for example, a printed-circuit board (PCB). During a packaging process for forming a package structure having the semiconductor dies and the external device, several depositing, etching, and heating operations may be performed. In such a packaging process, substrate warpage is a common problem that often occurs due to different thermal expansion coefficients of a variety of layers in the semiconductor dies. A solution to tackle the problem is required.